The present invention relates to a feeding system in a semiconductor integrated circuit device. More particularly, it relates to techniques which are effective when utilized for the feeding system of an integrated logic circuit employing emitter-coupled logic (ECL).
One form of semiconductor integrated circuit device is a semiconductor logic circuit wherein emitter-coupled logic (ECL) circuits are employed as gate circuits. By way of example, each of the ECL circuits includes a current switch circuit and an emitter follower circuit. The current switch circuit includes at least one input bipolar transistor which receives an input signal at its base, a bipolar transistor for reference whose emitter is coupled to the emitter of the input bipolar transistor and which receives a reference potential V.sub.BB at its base, a first load resistance which is interposed between the collector of the input bipolar transistor and a first supply voltage (Vcc) wiring line, a second load resistance which is interposed between the collector of the reference bipolar transistor and the supply voltage (Vcc) wiring line, and a current source which is interposed between the common emitters of the input and reference bipolar transistors and a second supply voltage (Vee) wiring line. On the other hand, the emitter follower circuit includes an emitter follower bipolar transistor whose base is coupled to the common node of the first load resistance and the collector of the input bipolar transistor, whose collector is coupled to the first supply voltage (Vcc) wiring line, and whose emitter is coupled to an output terminal and is also coupled to the second supply voltage (Vee) wiring line through an emitter resistance.
Japanese Patent Application Laid-Open No. 280348/1989 discloses a technique in a semiconductor memory circuit device having an ECL output circuit, according to which the supply voltage feed line of the emitter follower type output circuit portion of the ECL output circuit and the supply voltage feed line of an active circuit (current switch) forming the preceding stage of this output circuit portion are connected by a low impedance within a chip, thereby to prevent the output circuit portion from oscillating due to the inductance component of a lead terminal.
Before the present invention, the inventors made a study on the prevention of the malfunctions of the ECL circuit attributed to power source noise. As a result, it has been found out that a technique to be stated below is effective.
The current switch circuit is regarded as causing current produced from the current source, to flow from the first supply voltage wiring line to the second supply voltage wiring line steadily during its operation. On the other hand, the emitter follower circuit sends a great current from the first supply voltage wiring line to the output terminal (internal output terminal) of the ECL circuit when the output terminal is set at a high level. At this time, a potential level on the first supply voltage wiring line fluctuates because a parasitic inductance not being negligible is existent in the first supply voltage wiring line. Thus, when the fluctuation of the voltage level is transmitted to the current switch circuit through the first supply voltage wiring line, it degrades an A.C. noise margin for the input signal of the current switch circuit. Therefore, the inventors have developed the technique in which a first supply voltage wiring line for the current switch circuit and a first supply voltage wiring line for the emitter follower circuit are separately laid within the semiconductor chip, whereby the fluctuation of the voltage level (the power source noise) based on the operation of the emitter follower circuit is made less liable to be transmitted to the current switch circuit. In this case, the semiconductor chip is provided thereon with a first power source pad for feeding the first supply voltage (Vcc) to the first supply voltage wiring line of the current switch circuit, and a second power source pad for feeding the first supply voltage (Vcc) to the first supply voltage wiring line of the emitter follower circuit.